Chip on Board (COB): A Complete Manufacturing Guide

Published: May 2026 | Reading time: 13 minutes | Difficulty: Intermediate | Category: PCB Manufacturing

---

TL;DR / Key Takeaways

• Chip on board (COB) is a semiconductor packaging method that mounts bare silicon dies directly onto a PCB substrate without individual chip packages, using wire bonding or flip-chip connections sealed under epoxy resin
• The COB manufacturing process has four core stages: PCB substrate preparation → die attach → wire bonding → epoxy encapsulation
• COB delivers superior thermal dissipation (up to 30% lower operating temperature), 38× higher LED packing density than standard packages, and 0.5% annual failure rate for LED modules
• The key limitation is repairability — once the epoxy encapsulant is cured, a failed chip cannot be removed and the board must be scrapped
• COB dominates in LED lighting arrays, smart meters, camera modules, automotive ECUs, and IoT sensors

---

Table of Contents

1. What Is Chip on Board (COB)?
2. The COB vs SMD vs Flip Chip Decision
3. Step 1 — Prepare the PCB Substrate
4. Step 2 — Die Attach (Chip Placement)
5. Step 3 — Wire Bonding
6. Step 4 — Epoxy Encapsulation
7. Step 5 — Cure and Testing
8. Design for Manufacturing (DFM) Rules
9. Real-World Applications
10. Frequently Asked Questions

---

1. What Is Chip on Board (COB)?

Chip on board (COB) is a semiconductor packaging and PCB assembly technology that places bare, unpackaged silicon dies directly onto a printed circuit board substrate, connects them using fine wire bonds or flip-chip solder bumps, and seals them under a protective epoxy encapsulant — all without the intermediate chip packaging step used in conventional surface mount technology.

In conventional SMD assembly, each semiconductor chip is first encapsulated in a plastic or ceramic package (DIP, SOIC, QFP, BGA, etc.) before being placed and soldered onto the PCB. The package adds thickness, introduces parasitic inductance and capacitance in the signal path, and creates a thermal barrier between the silicon junction and the PCB heat spreader. Chip on board eliminates this intermediate package entirely: the bare die — a thin slice of silicon typically 150–750µm thick — is attached directly to the board.

COB is sometimes called “level 1.5 packaging” because it bridges the gap between individual component packaging (level 1) and full wafer-level or system-on-chip integration (level 2+). It captures the cost and thermal benefits of bare-die integration without requiring the massive capital investment of full wafer-level packaging.

The Black Blob Explained

The characteristic black epoxy blob covering a chip on board is called a glob-top encapsulant. It is not just cosmetic — it serves three critical functions:

1. Electrical insulation — prevents short circuits between the fine wire bonds and the surrounding environment
2. Physical protection — shields the fragile wire bonds and die surface from mechanical shock, vibration, and moisture ingress
3. Moisture barrier — prevents hydrolytic degradation of the silicon and wire bond interfaces over time

---

2. The COB vs SMD vs Flip Chip Decision

Understanding where chip on board fits relative to surface mount technology and flip-chip bonding is essential for selecting the right approach:

Comparison of Packaging Technologies

Connection	Reflow solder (paste + oven)	Wire bonding or flip chip	Solder bumps (TCB or reflow)
Typical pitch	0.3mm–0.65mm	25µm–100µm (wire bond)	0.15mm–0.5mm (bump pitch)
Thermal path	Through package → solder joint → board	Direct die attach → board	Direct bump → substrate
Repairability	Easy (hot air rework)	Nearly impossible (epoxy sealed)	Very difficult
Equipment cost	Low–medium	Medium–high	Very high
Volume economics	Excellent at any volume	Best at high volume	Best for high-I/O dies
Applications	General-purpose PCBs	LED arrays, smart meters, IoT	CPUs, GPUs, memory, RF

When to Choose COB

COB is the right choice when:

• Miniaturization is critical — the board must be as thin as possible (often under 1mm total thickness)
• Thermal performance matters — direct die-to-substrate attachment gives the shortest possible thermal path
• High-volume production — the per-unit cost advantage of eliminating chip packaging is most pronounced at scale
• LED or display applications — COB LED arrays achieve packing densities impossible with SMD packages
• Cost sensitivity — COB removes the cost of chip packaging, lead frames, and intermediate testing

---

3. Step 1 — Prepare the PCB Substrate

Core objective: Ensure the PCB surface is ready for direct die attachment with reliable bond pad metallurgy.

Surface Finish Requirements

The bond pads on a COB PCB must have a surface finish that supports reliable wire bonding or flip-chip attachment. Standard HASL (Hot Air Solder Leveling) is not suitable for chip on board — the uneven surface and lead content prevent reliable bond formation. Instead, COB PCBs use:

**Hard Gold**	99.9% gold over nickel	Gold wire only	For high-reliability applications; 25µm+ gold
**Immersion Silver**	Thin silver over copper	Aluminum wire	Lower cost alternative to ENIG
**ENEPIG**	Ni/Au/Pd over copper	Gold and aluminum wire	Best overall compatibility; used in medical/aerospace

The immersion gold layer on ENIG-finished boards must be thin (0.05–0.1µm) — if it is too thick, the gold absorbs too much heat during bonding and prevents proper intermetallic formation between the wire and the pad.

Substrate Material Selection

Standard FR-4 is acceptable for simple COB assemblies, but advanced applications require low-CTE substrates to minimize thermal stress at the die-attach interface. The CTE (Coefficient of Thermal Expansion) mismatch between silicon (~3 ppm/°C) and standard FR-4 (~14–18 ppm/°C) creates significant stress during thermal cycling.

Specialized low-CTE materials for COB:

RO4835 (PTFE + ceramic)	**8 ppm/°C**	High-frequency digital COB
Aluminum nitride (AIN)	**4–5 ppm/°C**	High-power LED COB, matches silicon closely
Polyimide flex	**12–20 ppm/°C**	Flexible COB for wearable and medical devices
Silicon interposer	**3 ppm/°C**	Buffer layer between die and PCB for stress-sensitive dies

Pad Design for Wire Bonding

Wire bonding pads must be sized to allow the bonding tool (a capillary or wedge) to contact each pad individually without touching adjacent pads:

• Pad size: Typically 75µm × 75µm minimum for gold wire bonding at 25µm pitch
• Pad spacing: Must accommodate the bonding tool diameter — typically 50µm clearance between adjacent pads
• Pad shape: Square or rectangular, with rounded corners to prevent stress concentration
• Solder mask: Typically omitted over bond pads; if present, it must be fully cleared from the pad area

---

4. Step 2 — Die Attach (Chip Placement)

Core objective: Bond the bare silicon die to the PCB substrate with precise placement and appropriate adhesive selection.

Die Preparation

Before placement, bare dice are typically delivered on a adhesive film on a wafer dicing ring (blue tape), or in waffle packs or Gel-Pak carriers. The dice are inspected under magnification for:

• Cracks or chips on the die edges (dicing defects)
• Surface contamination or particles
• Proper die attach pad metallization
• Backside metallization (if using conductive adhesive)

Adhesive Types for Die Attach

The choice of die attach adhesive depends on thermal, electrical, and processing requirements:

**Non-conductive epoxy**	Electrically insulating	150°C / 30–60min	Signal dies where insulation between die backside and board is needed
**UV-cure adhesive**	Non-conductive	365nm UV, 30–60sec	Fast production; limited thermal dissipation
**Thermoplastic die attach film**	Variable	Lamination at 150–200°C	Thin-package applications; uniform bond line

Silver-filled conductive adhesives (silver epoxy) are the most common choice for COB LED and power modules because they simultaneously provide electrical grounding of the die backside and thermal conduction to the PCB copper plane.

Placement Process

1. Clean the substrate — PCB surface is cleaned with IPA (isopropyl alcohol) and dried; any residue reduces adhesive bond strength
2. Apply adhesive — dispensed in a controlled amount at the die attach site using a pneumatic or auger dispenser; the adhesive volume must be sufficient to cover the full die footprint without overflow onto bond pads
3. Die pick-and-place — a precision pick-and-place machine or operator uses a vacuum collet to pick the die from its carrier and place it onto the adhesive; placement accuracy: ±25µm (3-sigma) for standard dies
4. Adhesive cure — the assembly goes into a curing oven per the adhesive manufacturer’s profile; conductive silver epoxy is typically cured at 120°C for 2 hours or 150°C for 1 hour
5. Bond pull test — a sample from each lot is tested per MIL-STD-883 (method 2011) to verify die attach strength

---

5. Step 3 — Wire Bonding

Core objective: Create reliable electrical connections between the die pads and the PCB bond pads using fine metal wires.

Wire bonding is the heart of chip on board assembly. It creates individual electrical connections from each bond pad on the die to the corresponding pad on the PCB, enabling power, ground, and signal distribution.

Wire Bonding Methods

Two primary bonding methods are used in COB assembly:

Thermosonic bonding (TS) — The most common method, using a combination of ultrasonic energy, elevated temperature (typically 100–150°C), and mechanical force through a tungsten carbide or ruby capillary tool. Gold wire is bonded to gold-plated or aluminum pads. This is the process used in the SparkFun multimeter factory video referenced by industry analysts: the automated wire bonder visually identifies pad locations, then bonds each wire individually at 10–20 bonds per second.

Ultrasonic bonding (US) — Uses only ultrasonic energy and mechanical force at room temperature. Primarily used with aluminum wire on aluminum or gold-plated pads. Common in high-reliability military and aerospace COB assemblies where the heat of thermosonic bonding could damage temperature-sensitive dice.

Wire Specifications

Breaking load	3–15gf depending on diameter	10–50gf
Conductivity	Very high	High
Cost	Higher	Lower
Primary use	Consumer, LED, smart meters	Military, high-reliability aerospace

Gold wire (99.99% purity, typically 4N or 6N grade) is the most common in commercial COB production because it forms reliable bonds on both gold-plated ENIG pads and aluminum pads without intermetallic compound issues that affect aluminum wire on gold pads.

Wire Bond Process

1. First bond (die side) — The capillary tool descends to the die pad, applies heat and ultrasonic energy, and forms a ball bond (a small gold sphere fused to the pad surface). The ball bond is typically 2.5–3× the wire diameter.
2. Wire loop formation — The wire is drawn up and across to the PCB pad location, forming a controlled loop height and shape. Loop heights typically range from 100–300µm above the die surface.
3. Second bond (substrate side) — The tool forms a stitch bond (wedge bond) on the PCB pad, simultaneously clamping and cutting the wire. The stitch bond is mechanically wedge-shaped.
4. Tail and re-bond — The tool moves to the next die pad, forms a new ball bond, and the process repeats.

A typical COB IC with 41 connections (like the smart meter controller referenced in factory documentation) requires 41 individual bond cycles on the automated bonder. Modern wire bonders operate at 10–20 bonds per second, completing a 41-bond die in approximately 2–4 seconds of bonding time.

Thermocompression Bonding (Flip Chip Variant)

For flip-chip COB variants, thermocompression bonding replaces wire bonding. In this process:

1. The die is flipped (face down) onto the PCB
2. Solder bumps on the die pads (or on the substrate pads) are reflowed
3. The assembly is heated to the solder reflow temperature while pressure is applied
4. A strong metallurgical bond forms at each bump pad interface

Thermocompression bonding for flip-chip COB creates bonds that are mechanically stronger than standard solder joints and eliminates the inductance and parasitic capacitance of wire bonds — making it preferred for RF and high-speed digital applications.

---

6. Step 4 — Epoxy Encapsulation

Core objective: Seal the die and wire bonds under a protective epoxy layer that provides electrical insulation, mechanical protection, and moisture resistance.

Encapsulant Types

The epoxy compound applied over the die and wire bonds in chip on board assembly is called glob-top. The viscosity, cure profile, and material properties of the encapsulant are chosen based on the specific application requirements:

**Glass transition temperature (Tg)**	80–150°C	Must remain mechanically stable at the highest operating temperature
**CTE (below Tg)**	25–45 ppm/°C	Must be close to the silicon and PCB CTE to minimize thermal stress
**Water absorption**	< 0.5%	Moisture absorbed by the encapsulant causes delamination and corrosion
**Flame retardancy**	UL94 V-0	Required for consumer and automotive safety certifications
**Thermal conductivity**	0.5–2.0 W/mK	Higher for power devices; helps heat flow from die to PCB

Encapsulation Process

1. Viscosity check — The encapsulant is mixed (if two-part) and its viscosity verified; viscosity that is too high prevents flow under the die, while viscosity too low causes the material to wick between bond pads and create short circuits
2. Dispensing — A precision dispenser (automated or semi-automatic) deposits a measured amount of epoxy directly over the die and wire bonding area; a dam may be built around the area first (dam-and-fill process) for more controlled coverage
3. Flow control — The viscosity must be carefully controlled to prevent the encapsulant from wicking between adjacent wire bonds (which would create an electrical short) or from pulling away from the die edges (which would leave gaps)
4. Leveling — For flat-top glob-top, a spreading tool levels the epoxy surface; for raised glob-top, no leveling is applied

Cure Profile

After dispensing, the epoxy encapsulant is cured in a convection oven:

Ramp	85°C → 125°C	30 min	Slow cure initiation
Hold	125°C	60–120 min	Full cure crosslinking
Cool	125°C → 40°C	30 min	Controlled cooldown to prevent stress

For UV-cure encapsulants, the cure step is replaced by UV exposure (365nm at 1,000–5,000 mJ/cm²) followed by a short thermal post-cure for complete crosslinking.

---

7. Step 5 — Cure and Testing

Core objective: Complete the encapsulation cure and verify the COB assembly meets electrical and mechanical specifications before it proceeds to final assembly.

Electrical Testing

After encapsulation cure, every COB assembly undergoes:

1. Continuity test — Verify all wire bonds are intact and no open circuits exist at the die or substrate bond points. This is typically done with a flying probe tester or in-circuit test fixture.
2. Insulation resistance test — Verify no short circuits between adjacent bonds, between bonds and the die backside, or between any net and ground. Minimum acceptable resistance is typically 100MΩ at 100V DC.
3. Functional test — For smart meter ICs, LED arrays, or other functional COB assemblies, the full electrical function of the chip is verified at this stage. A failed functional test after cure means the entire board is scrapped.
4. Burn-in test (optional, for high-reliability applications) — The assembly is powered and operated at elevated temperature (typically 85°C, 85% RH) for 24–168 hours to accelerate latent failure modes before shipment.

Visual Inspection

• 100% inspection of the encapsulant dome under magnification for voids, delamination, cracks, or contamination
• X-ray inspection (if available) to verify wire bond loop integrity under the encapsulant, particularly for fine-pitch dies
• Acoustic microscopy (C-SAM) for delamination detection at the die-attach interface — critical for power devices and automotive applications

Quality Standards

COB assemblies for commercial applications must meet IPC Class 2 standards (general electronics), while automotive and medical applications require IPC Class 3 (high-reliability) compliance. Key requirements include:

• Wire pull strength per MIL-STD-883 Method 2011: minimum 3gf for 25µm gold wire
• Die shear strength per MIL-STD-883 Method 2019: minimum 2kgf for a 1mm² die
• Encapsulant adhesion: no delamination visible at 10× magnification after 3 thermal cycles (-40°C to +125°C)

---

8. Design for Manufacturing (DFM) Rules

Designing a PCB for chip on board assembly requires following specific rules that differ significantly from standard SMD design:

PCB Layout DFM Checklist

Die attach pad size	Minimum 10% larger than die footprint	Allows for placement tolerance and adhesive squeeze-out
Bond pad size	75µm minimum per side	Must accommodate bonding tool capillary
Bond pad spacing	50µm minimum clearance	Prevents tool contact with adjacent pads during bonding
Wire routing	Minimum 25µm clearance between wire loops and adjacent bonds	Prevents wire-to-wire contact and shorts
Via placement under die	Tented or plugged	Open vias under die create voids in adhesive and reduce thermal performance
PCB cleanliness	Class 1000–10,000 cleanroom assembly	Particles cause bond failures and encapsulant voids
Thermal vias under die	0.3–0.5mm pitch, thermal relief array	Provides low-impedance heat path to inner copper planes
PCB thickness	0.8–1.6mm for most COB; 0.2–0.4mm for flex COB	Must support die attach process without flexing

Common COB Design Mistakes

1. Using HASL surface finish — The uneven solder surface prevents reliable wire bonding and causes inconsistent ball bond formation
2. Placing vias under the die attach area — Unfilled vias create voids in the adhesive, creating hot spots under the die
3. Insufficient thermal relief on power pads — Fully cleared copper around power die attach pads prevents heat spreading into the PCB copper plane
4. Insufficient clearance around bond pads — Bonding tool access requires clear space; silkscreen markings or traces too close to pads cause tool collision
5. Wrong encapsulant viscosity — Using a viscosity that is too low causes wicking between wire bonds, creating short circuits

---

9. Real-World Applications

Chip on board technology is found in virtually every electronic product category, often in places you would not expect:

LED Lighting and Displays

COB LED arrays are the dominant technology for high-power white light sources. A single COB LED module can contain hundreds of individual LED dice on a single substrate, producing over 15,000 lumens from a package the size of a postage stamp. Key advantages in LED applications:

• Packing density — 38× denser than individually packaged SMD LEDs (per Prophotonix benchmarks)
• Thermal efficiency — up to 30% lower operating temperature than equivalent SMD LED arrays
• Uniform light — No visible LED hotspots; light blends seamlessly from the densely packed chip array
• Lifespan — 100,000+ hours at rated operating conditions
• IP65 rating — Epoxy encapsulation provides inherent dust and water resistance

COB LEDs are used in stadium floodlights, automotive headlamps, surgical lighting, studio fresnels, and large-format direct-view LED displays with pixel pitches as fine as P0.9mm (0.9mm between pixel centers).

Smart Meters and Utility Electronics

The black blob on a digital multimeter’s main board is a COB-mounted smart meter controller IC. Manufacturing Economics Corporation and SparkFun factory documentation both document this: the chip-on-board smart meter controller costs 60–80% less than the equivalent packaged IC and is glued and wire-bonded directly to the PCB on the same production floor. The entire assembly — die attach, wire bonding, and epoxy glob-top — takes under 10 minutes per board.

Camera Modules

Every smartphone camera module uses COB or chip-scale packaging (CSP, a variant of COB) for the image sensor die. The sensor die is attached directly to a rigid or flex substrate, wire-bonded, and encapsulated — all in a package thinner than 5mm total height. Sony, Samsung, and OmniVision all manufacture image sensors using COB-style die attach for their mobile sensor lines.

Automotive Electronics

Automotive ECUs (Engine Control Units), infotainment systems, and LiDAR sensors increasingly use COB assemblies for their combination of miniaturization, thermal performance, and vibration resistance. COB assemblies in automotive applications must pass AEC-Q100 (IC) and IPC Class 3 (assembly) qualification, including temperature cycling from -40°C to +125°C, mechanical shock (50g, 11ms half-sine), and vibration testing.

Internet of Things (IoT) Sensors

Agricultural soil moisture sensors, biomedical implants, and industrial condition monitoring sensors use COB ASICs sealed in epoxy for long-term reliability in harsh environments. The solid epoxy encapsulation provides the IP67-rated moisture protection required for sensors that must operate for years in field deployment without maintenance.

---

10. Frequently Asked Questions

What is chip on board technology?

Chip on board (COB) is a semiconductor packaging method that mounts bare, unpackaged silicon dies directly onto a PCB substrate. The bare die is attached with conductive or non-conductive adhesive, connected to the PCB using fine gold or aluminum wire bonds (typically 25–50µm diameter), and sealed under an epoxy encapsulant called glob-top. This eliminates the intermediate chip packaging step used in conventional SMD assembly, resulting in thinner boards, shorter thermal paths, and lower per-unit cost at high production volumes. The technology is used in LED arrays, smart meters, camera modules, automotive ECUs, and IoT sensors.

How does chip on board work?

Chip on board works by placing a bare silicon die directly onto a prepared PCB surface, connecting each die bond pad to the corresponding PCB pad using fine wire bonds, and sealing the assembly under epoxy encapsulant. The process follows four stages: first, the PCB substrate is prepared with ENIG or hard gold surface finish and low-CTE materials to minimize thermal stress; second, the die is attached using conductive silver epoxy (for power applications) or non-conductive epoxy (for signal dies), cured at 120–150°C; third, a wire bonder creates individual electrical connections between die pads and PCB pads using thermosonic bonding (gold wire on heated substrate) or ultrasonic bonding (aluminum wire); fourth, epoxy encapsulant is dispensed over the die and bonds, then cured at 125°C for 1–2 hours. The result is a fully functional chip-level assembly directly integrated into the PCB without any intermediate chip package.

What are the advantages of COB over SMD?

COB offers five significant advantages over conventional surface mount technology: First, size reduction — eliminating the chip package removes 0.5–2.0mm of height and reduces board footprint; a COB assembly can be 40–60% thinner than the equivalent SMD packaged IC. Second, thermal performance — the die attaches directly to the PCB copper, creating a thermal path 5–10× shorter than through a package and solder joint; COB LED arrays operate at up to 30% lower junction temperature than SMD equivalents. Third, cost efficiency — at volumes above 10,000 units/year, COB eliminates the per-unit cost of chip packaging (typically $0.02–0.20 per lead for packaged ICs), reducing total component cost significantly. Fourth, reliability — fewer solder joints means fewer failure points; COB LED modules show 0.5% annual failure rate vs 1–2% for equivalent SMD arrays. Fifth, electrical performance — shorter interconnects reduce parasitic inductance and capacitance, improving signal integrity at high frequencies and in RF applications.

What are the disadvantages of chip on board?

The primary disadvantage of chip on board is irreversible repairability — once the epoxy encapsulant is cured, the die and wire bonds cannot be removed without destroying them. If the COB die fails electrical testing or in the field, the entire PCB must typically be scrapped. This makes yield control critical: COB manufacturers must catch defects before encapsulation or accept full board loss. Second, COB requires higher equipment investment than standard SMD assembly — a precision die attach system ($50,000–200,000) and automated wire bonder ($100,000–500,000) are needed for production volumes, compared to a basic pick-and-place ($20,000–50,000) for SMD. Third, bare die supply chain complexity — bare dice must often be procured directly from semiconductor foundries rather than through distributors, adding procurement lead time and minimum order quantities. Fourth, CTE mismatch stress — the large thermal expansion coefficient difference between silicon (3 ppm/°C) and standard PCB substrate (14–18 ppm/°C) creates mechanical stress at the die-attach interface during thermal cycling, which can cause crack propagation over time.

What is wire bonding in COB?

Wire bonding in chip on board is the process of creating individual electrical connections between the bond pads on the bare silicon die and the corresponding pads on the PCB using fine metal wires. In thermosonic (gold) wire bonding — the most common COB process — a 15–50µm diameter gold wire is fed through a capillary tool, a precision ball is formed at the tip using electronic flame-off (EFO), the ball is pressed onto the die pad under heat (100–150°C) and ultrasonic energy, the wire is drawn to the PCB pad, and a stitch bond is formed there. A single COB IC with 41 connections (as documented in smart meter controller assemblies) requires 41 individual bond operations on the automated wire bonder, taking approximately 2–4 seconds total. Wire bonds are the weakest mechanical link in a COB assembly and must meet MIL-STD-883 Method 2011 minimum pull strength requirements.

What materials are used in COB PCB substrate?

COB PCB substrates use specialized materials beyond standard FR-4 to address the thermal expansion coefficient (CTE) mismatch between silicon (~3 ppm/°C) and the board material. For general-purpose COB, standard FR-4 with ENIG finish is acceptable if thermal cycling requirements are moderate. For high-performance applications, engineers specify: RO3003 (PTFE laminate with ceramic filler, CTE = 6 ppm/°C) for RF and microwave COB; RO4835 (similar construction, CTE = 8 ppm/°C) for high-frequency digital COB; aluminum nitride (AIN) substrate (CTE = 4–5 ppm/°C, matching silicon closely) for high-power LED and automotive COB; polyimide flex circuits for wearable and medical COB applications; and silicon interposers as a buffer layer between the die and PCB for stress-sensitive dies. The ENIG surface finish (electroless nickel / immersion gold, gold thickness 0.05–0.1µm) is the standard pad finish for COB because it provides a solderable and bondable surface compatible with both gold and aluminum wire bonding processes.

---

Conclusion

Chip on board (COB) technology is a cornerstone of modern miniaturized electronics — from the LED arrays illuminating stadiums to the smart meter controllers in your garage and the camera modules in smartphones. Its core appeal is straightforward: by eliminating the chip package, COB makes electronics smaller, cooler, and cheaper to manufacture at scale.

The practical principles to remember:

• Choose COB when miniaturization and thermal performance are the top priorities — and when repairability is not a requirement
• Invest in substrate preparation — ENIG finish and low-CTE materials prevent the thermal stress that is COB’s most persistent reliability threat
• Wire bonding quality determines COB reliability — bond strength, loop control, and pad design must meet IPC Class 2 or 3 standards
• Viscosity control during encapsulation is critical — too high and the encapsulant voids; too low and it shorts the wire bonds
• Yield before encapsulation is everything — test electrically before the epoxy cures, because post-encapsulation failure means board scrap

With these principles in mind, chip on board is one of the most powerful tools in the PCB engineer’s toolkit for achieving high density, high performance, and high volume in a single assembly technology.